The present invention relates to semiconductor memory devices comprising silicon-rich amorphous silicon alloy memory elements which are electrically-programmable through current induced conductivity.
A semiconductor memory device of the above kind is described in PCT WO 96/19837. The memory elements in this device comprise a layer of hydrogenated, silicon rich amorphous silicon alloy material, containing at least one other element in addition to hydrogen and silicon, for example nitrogen or carbon, which material is sandwiched between a pair of electrically conductive contact layers. The memory element is programmed by inducing a defect band throughout a region of the amorphous silicon alloy layer, for example by electrical current stressing, which lowers the activation energy for the transport of carriers in the layer by a selected amount which can be varied. By tailoring this defect band, or more specifically the concentration and distribution of energies of the defects in the defect band, the extent of the lowering of the activation energy level of the element can be selectively set to programme the element. The memory element is effectively an analogue memory element as the amount of activation energy lowering can be selected from a more or less continuous range rather than just two states. The memory elements differ from other known thin film memory elements using amorphous silicon alloy material of the so-called filamentary kind in which a localised filamentary region is produced by a so-called forming process which causes, it is believed, a top metal contact to diffuse into the doped amorphous silicon layer, in that their structure and operation does not involve or depend on the presence of filaments. Rather, the induced defect band leads to the element having a bulk controlled effect which is proportional to its area. These memory elements are highly reproducible and are capable of being programmed over a comparatively wide range, for example around three orders of magnitude or more. When fabricated in an array on a common substrate using common-deposited layers, the behaviour of individual memory elements is highly predictable and similar. Aforementioned PCT WO 96/19837 describes embodiments of memory devices comprising arrays of such memory elements. The memory elements are arranged in a 2D matrix array on a substrate and addressed via crossing sets of row and column conductors, with individual memory elements being defined at the respective intersections of the row and column address conductors. The array of memory elements is fabricated by depositing a layer of conductive material over the substrate, photolithographically patterning this layer to define one set of address conductors, depositing a continuous layer of the amorphous silicon alloy material over these conductors and then depositing a further layer of conductive material over the amorphous silicon alloy layer and photolithographically patterning this layer to define the other set of address conductors. A plurality of 2D arrays of memory elements stacked upon one another is produced successively in this manner to form a multi-level memory array device with each array having sets of address conductors. A set of address conductors associated with one array may serve also as one set of address conductors for an adjacent array. In this structure, therefore, each memory element in one array is individually addressable and each array of memory elements is addressed separately. The storage capacity of the memory device is thus determined by the number of memory elements in each array and the number of arrays.